When determining the behaviour of a system on chip in a test system, data traffic or vectors are generated for input into a model of at least some of the system including the interconnect connecting the various devices and the resulting performance of the system is analysed. The model may be a software model or it may be a circuit built perhaps out of field programmable gate arrays, FPGA to model the system or it may be an emulator.
The data traffic may be generated from real data traffic by tracing a data stream on a bus of a real system, this trace data then being replayed and input to the test system, or it may be example data traffic generated by a model that models the initiators of the system and generates example data traffic as a probability representative of what requests will be sent at what time.
A problem with this is that the dependencies between the transactions within the initiators such as the CPU's or the GPU's are generally not captured. However, dependencies within these devices cause their performance to vary as properties of the environment in which they are connected change. Thus, although the data traffic may be representative of a system at a certain point, if the system is amended in some way and then re-tested the results may no longer be representative as any dependencies such as data dependencies arising within the initiator themselves will not be modelled and yet these may affect the performance. In particular, many initiators or masters are self-throttling, CPU's for example often need results to be sent back from the interconnect to be able to continue while GPU's generally don't and will be less affected by changes within the interconnect. Thus, if a CPU is unable to proceed without receiving the results of a load instruction for example, this delay may in turn further delay the issuing of subsequent load or store instructions. Changes in the system that affect this delay will therefore also affect the dependent functions and if this is not accounted for in the model the resulting modelled performance will no longer be representative.
One way of addressing this in the prior art has been with the use of adaptive trace in which the data representative of the data traffic on the bus that is input to the system contains realistic dependencies between the transactions. This is expensive to capture as you need to implement the actual system to know where the dependencies arise so that the masters of the system need to be masters that you can instrument.
It would be desirable to be able to model a system that takes some account of dependencies without unduly increasing the complexity or size of the model.